WORK OUT EVERY QUESTION KINDLY Write function that takes in a root…

Question Answered step-by-step WORK OUT EVERY QUESTION KINDLY Write function that takes in a root… WORK OUT EVERY QUESTION KINDLYWrite  function that takes in a root node of a trie and returns the length of the longest word stored in that trie.Create  C++ program to manage phone contactThe program will allow the user to add new phone contacts, display a list of all contacts, search for a specific contact by name, delete a specific contact.Write  C program that will handle and organize two parallel one-dimensional arraysWrite  C function to add a node to the beginning of a linked list. Consider the following definitions of the functionals foldl and foldr: fun foldl f e [] = e | foldl f e (h::t) = foldl f (f(h,e)) t; fun foldr f e [] = e | foldr f e (h::t) = f(h, foldr f e t); What is the type of foldl? [2 marks] What is the type of the expression foldr op/? [2 marks] For each of the following functions, write an ML definition using one of the functionals foldl or foldr. (a) product: (real list) -> real, which given a list of real numbers gives their product. (b) exists: (‘a -> bool) -> (‘a list) -> bool, which given a predicate p and a list l determines whether there is any element of l satisfying p. (c) length: (‘a list) -> int which determines the length of a list. [9 marks] Prove, by induction on lists, that for all lists of integers l, the following identity is true: foldl op+ 0 l = foldr op+ 0 l Explain the Bayesian approach to solving problems in computer vision. Explain the notion of an Inverse Problem and how computer vision can be regarded thereby in a formal sense as inverse graphics. Write down Bayes’ rule in general form, and explain the interpretation of its terms as: • probability of the image, given the object • probability of the object, given the image What is the role of the “prior?” Discuss and illustrate the Bayesian approach in terms of 3D surface reconstruction, given the reflectance data in an image. [20 marks] 8 CST.2000.12.9 13 Complexity Theory Give precise definitions of polynomial time reductions and NP-completeness. [2 marks each] Consider the following two decision problems on undirected graphs. 3-node-colourability: the collection of graphs G = (V, E) for which there is a mapping ? : V ? {r, g, b} such that if (u, v) ? E, then ?(u) 6= ?(v). 3-edge-colourability: the collection of graphs G = (V, E) for which there is a mapping ? : E ? {r, g, b} such that if (u, v),(u, v0 ) ? E, with v 6= v 0 , then ?(u, v) 6= ?(u, v0 ). Show that there is a polynomial time reduction from 3-edge-colourability to 3-node-colourability. [8 marks] The problem 3-edge-colourability is known to be NP-complete. Using this information, for each of the following statements, state whether or not it is true. In each case, give complete justification for your answer. (a) There is a polynomial time reduction from 3-node-colourability to 3-ed   \\\\\\\\\\\\\\\\\\\\\\\\\    What pipeline hazards can they mitigate and what are the limitations of the mitigations? Provide one or more examples to illustrate the challenges. [8 marks](c) In detail, describe the hardware mechanisms that are required to support virtual memory for a pipelined processor implementing the 32-bit RISC-V ISA. [6 marks] 3 CST1.2021.5.4 3 Computer Design A processor contains two Each L1 is a direct-mapped, 4 KiB, write-back cache. The L2 is a 4-way set-associative 16 KiB cache with the least-recently-used replacement policy. All cache lines are 16 B long. The hierarchy is inclusive, runs the MSI cache coherence protocol and is initially empty. (a) Considering this cache hierarchy, (i) Explain whether it would be suitable for a system-on-chip that is only running single-threaded applications. [2 marks] (ii) Explain whether it would be suitable for a system-on-chip where each core processes a small (e.g. 6 1 KiB) array of data at a time. [2 marks] (b) Show the cache contents and coherence state of cache lines after each access in the following sequence of physical addresses, stating any assumptions you have made. All accesses are 4 bytes long and entirely complete before the next one starts. Core 1: Read 0xab18 Core 2: Read 0xdb14 Core 1: Write 0x1b10 Core 1: Read 0xab14 Core 1: Read 0xbb1c Core 2: Write 0xa010 Core 1: Read 0x2b10 Core 2: Read 0x1b10 Core 1: Read 0xa018 Core 1: Write 0x1b14 [8 marks] (c) Describe the impact of each change below (in isolation) on the cache hierarchy. (i) Increasing the L1 cache size. (ii) Increasing the line size in all caches. (iii) Increasing the associativity of the L1 caches. (iv) Changing to an exclusive cache hierarchy. A local area network may carry several different LANs simultaneously; such anetwork would be designated for known sets of HomePlug devices.Describe a physical line coding approach for the HomePlug devices that: allowstwo or more simultaneous virtual local area networks to fairly share the samephysical channel, but does not permit trivial interception of network traffic.Outline your approach along with its benefits and drawbacks, comparing it withthe simplest use of VLAN tags in Ethernet.  (a) Explain what is meant by “instruction scheduling” in a compiler. Indicatewhat properties of architectures make it beneficial. Are some architecturestoo simple, or too complex, for it to be useful? [3 marks](b) Sketch an algorithm that schedules instructions within a basic block for anarchitecture of your choice on which scheduling is useful. Indicate its timecomplexity O(f(n)) stating to what ‘n’ refers. What additional complicationsarise in choosing which instruction to emit first from a basic block? [5 marks](c) Indicate how your algorithm could be modified to deal with a static multipleissue VLIW-style architecture. The input basic block contains simpleinstructions, but the output basic block contains wide instructions consisting oftwo simple instructions (either of which may be NOP). These two instructionsexecute in parallel.Now explain how your algorithm can schedule the following sequence ofinstructions to execute in parallel, or detail any adjustments necessary topermit this.st r1,4(r8)ld r2,0(r8)Explain how alias analysis or points-to analysis might provide information tothe instruction scheduler to enable a wider range of load/store pairs to bere-scheduled. [6 marks](d) Briefly summarise a source-level approach to alias or points-to analysis, forexample Andersen’s algorithm. Your summary should emphasise key choices,for example any data-structures used; detailed algorithms are not required.[6 marks]9 (TURN OVER)CST.2011.9.109 Principles of Communications(a) Control Theory allows us to find various useful properties of a system such asstability. Draw a picture of a generic control system, explaining the functionsof feedback and the design goals for the controller. [5 marks](b) The Transmission Control Protocol of the Internet uses a feedback controllerand responds to absence or presence of congestion signals by Additive IncreaseMultiplicative Decrease of a sending window.(i) Describe the operation of this scheme. [10 marks](ii) Explain qualitatively why the scheme is necessary, but perhaps notsufficient, to create  stable set of traffic flows in the Internet. [5 marks]10 System-on-Chip Design(a) What is an instruction set simulator (ISS) and what is typically the best wayfor it to achieve high performance? [2 marks](b) What performance bottleneck can typically arise when CPU-intensive softwareis run on a model of a complete system on chip (SoC)? How can this be avoidedand at what costs to modelling accuracy? [4 marks](c) What problems can arise when operating system device drivers are run on anISS that has been optimised according to your answers to parts (a) and (b)above? [4 marks](d) Two processors on a SoC have separate address spaces. What does this mean?Describe a simple hardware mechanism for sending non-trivial amounts of databetween processors in separate address spaces. Interrupts should be used.[4 marks](e) Briefly describe both a high-level and a mid-level model of your answer topart (d) where the mid-level model requires minimal or no modification to thedevice driver firmware but is not a net-level model and where the high-levelmodel dispenses with much of the device driver code and many or all of theinterrupts. (a) Explain what happens to the state space, the possible behaviours and thereachable state space when two automata are coupled. [3 marks](b) The Banker’s Algorithm can be viewed as a predicate over shared state. Whatstate does it operate over and does this include the program counter of theparticipating threads? When does it return true or false? [6 marks](c) What is the difference between strict and non-strict isolation in a transactionprocessing system? What do both approaches ensure? Which can lead to atransaction abort being forced by the system and why? [3 marks](d) “Increment and decrement operations are freely commutable” — what twoassumptions are required for this statement to hold? Is it true that theeffects of transactions containing increment and decrement operations are alwaysserialisable? [3 marks](e) Customers interact with a transaction processing system over a web interfacebut confirmations are also sent by, such as ‘please collect from your localbranch’.generated before, during, or after the process ofcommitting the order transaction? What are the advantages and disadvantagesof different approaches? Fully justify at least two design decisions in terms ofsystem complexity and durability over a system crash.[5 marks]8CST1.2021.5.98 Concurrent and Distributed SystemsYou are developing a distributed system in which you want some task to be assignedto exactly one node at any given time. If that node crashes, the task must beautomatically reassigned to a different node, but you also want to ensure that thereare never two or more nodes executing the task at the same time.This is known as a lease. A lease is a concurrency primitive similar to a lock (onlyone node may hold a lease at any time); the difference is that a lease times out if itis not renewed for some time. After timing out, another node can acquire the lease.(a) Briefly summarise how leader election works in the Raft consensus algorithm,and discuss the commonalities and differences between leader election and alease. (Focus only on leader election, and ignore the rest of the Raft algorithm.Include the role of the term number in your explanation.) [5 marks](b) In a partially-synchronous system with crash-recovery failures, is it possible toguarantee that a lease is always held by exactly one node? Justify your answer.[5 marks](c) You are asked to design a lease algorithm for a system in which the set of nodes isnot known in advance, and may change over time. Can the Raft leader electionalgorithm be used here? Why/why not? Describe how graph-based backjumping would behave in the situation describedin part (b). Does it backjump to the same place? Why might graph-basedbackjumping in general be preferred to Gaschnig’s algorithm? [6 marks](d) Describe how forward checking would deal with the sequence of assignmentsgiven in part (b). How does the effectiveness of backjumping compare with thatof forward checking in this case? [5 marks]3 (TURN OVER)CST.2012.4.43 Computer Graphics and Image Processing(a) What are the main criteria to be considered in the design of a line drawingalgorithm for a raster graphics display? [2 marks](b) Describe an algorithm to fill a series of pixels running from (x0, y0) to (x1, y1)that meets these criteria, explaining why it does so. Answers should consist ofmore than a fragment of pseudo-code. [6 marks](c) A new volumetric display stores an image as a three-dimensional array ofvolume elements or voxels. Reformulate the design and implementation ofthe line-drawing algorithm to fill a series of voxels running from (x0, y0, z0) to(x1, y1, z1). [6 marks](d) How would this line-drawing algorithm be used to draw B´ezier curves in threedimensions? [6 marks]4WORK OUT EVERY QUESTION KINDLY  Computer Science Engineering & Technology Object-Oriented Programming POLS 206 Share QuestionEmailCopy link Comments (0)