(i) A competitive Kohonen neural network forms feature maps which…

Question Answered step-by-step (i) A competitive Kohonen neural network forms feature maps which…  (i) A competitive Kohonen neural network forms feature maps which can beregarded as performing dimensionality reduction. Explain this.[4 marks](ii) Is training time normally faster, or slower, in a supervised neural networkcompared with an unsupervised one? What is the major disadvantageinherent in the use of supervised neural networks? [2 marks](iii) What class of neural network can be used to overcome the mathematicaldifficulties caused by the use of non-orthogonal sensory and motorrepresentations? [2 marks](b) (i) Give three examples of biological sensory or motor control systems thatseem to rely on the use of non-orthogonal coordinates. [3 marks](ii) Explain why this creates a problem in the computational evaluation andsimulation of such systems, and discuss whether or not you think thisissue matters in the function of the actual neurobiological systems.[2 marks](c) (i) Give four examples of neural activity having a fundamentally quantalstructure, in the sense that signals or events are quantised into discretepackages rather than being continuous. [4 marks](ii) For purposes of understanding neurobiological computation, what canbe learned from studying the brain’s failures, either as the consequencesof specific forms of trauma or in normal function as revealed in thesystematic visual illusions? [3 marks]7 [TURN OVERCST.2001.8.810 Comparative ArchitecturesAn important application spends a large proportion of its running time executing aparticular loop. The loop is responsible for summing two arrays containing unsignedeight-bit values packed in memory into a similar third array. Saturating arithmeticis used, whereby results that overflow are “clipped” to the maximum representablevalue. For example, for the unsigned eight-bit case, 250 plus 20 would result in 255.In this particular application, such overflows are rare in practice, and this fact maybe exploited to optimise the implementation.(a) Write pseudo code for a simple implementation of the inner loop for a 32-bit processor with a RISC-like instruction set. [Hint: It is possible to usethe CPU’s 32-bit ALU to perform four eight-bit additions with a single addinstruction, and then use further code to detect if overflow occurred and correctit. You may assume the arrays start on word-aligned boundaries.] [10 marks](b) Assuming the arrays are present in the CPU’s L1 data cache, estimate thenumber of cycles required to sum arrays of length N on a statically-scheduledtwo-way super-scalar processor. State any assumptions you make. [5 marks](c) Many instruction set architectures have been augmented with SIMD (SingleInstruction Multiple Data) instructions to enhance processors’ performancewhen dealing with packed arrays such as those used by this application.Demonstrate how SIMD instructions could be used to optimise the loop.Assuming that 50% of the running time of the application was spent executingyour previous loop implementation, estimate the program’s speedup whenusing the SIMD optimised loop.RKImage transcription textThere are 18 mathematics majors and325 computer science majors at acollege. If one True/False … Show more… Show moreImage transcription textExercise 9.1. Write the followingstatement in a symbolic form with theindicated letters to repre… Show more… Show more  Computer Science Engineering & Technology C++ Programming COMPUTER S 167A Share QuestionEmailCopy link Comments (0)